1. Field of the Invention
The present invention relates to a nonvolatile memory such as a flash memory including memory transistors each having a floating gate, and more particularly to an improvement in the memory to reduce the time needed for writing data into the memory transistors.
2. Description of Related Art
FIG. 7 is a block diagram showing a conventional flash memory and a configuration for writing data into it. In FIG. 7, the reference numeral 1 designates a flash memory; 2 designates a tester for writing data into the flash memory 1; and 3 designates an external data bus for interconnecting them. The reference numeral 4 designates a memory cell array including a plurality of memory transistors; 5 designates a data port for interconnecting the memory cell array 4 with the external data bus 3; and 6 designates an address input port for selecting from the memory cell array 4 memory transistors to be connected to the data port 5. The reference numeral 7 designates a tester side data port connected to the external data bus 3; 8 designates a write data memory for storing write data to be output from the tester side data port 7; 9 designates a read data memory 9 for storing write verify data supplied from the tester side data port 7; 10 designates an address generator for selecting a data write/read address; and 11 designates a write controller for controlling the blocks 7, 8, 9 and 10, thereby having the memory cell array 4 store the data in the write data memory 8.
Next, the operation of the conventional system will be described.
When data to be written is stored in the write data memory 8 of the tester 2, the write controller 11 starts to write the data. Specifically, it carries out control such that the address generator 10 generates a write start address, and the tester side data port 7 sets the data to be written in the address. Thus, the flash memory 1 sequentially selects the memory transistors corresponding to the address, and performs charge injection to the floating gates of the memory transistors in accordance with the input data.
When completing the data write, the write controller 11 has the address generator 10 generate that address again to which the data is written. In response to this, the flash memory 1 reads the data from the memory transistors of that address, and outputs it from the data port 5. The write controller 11 has the read data memory 9 store the data through the tester side data port 7. Afterward, it carries out verify check by comparing for each address the data stored in the write data memory 8 with the data stored in the read data memory 9. When all the memory transistors store the data correctly, it completes the data write, whereas if any error is detected in any transistor, the data write and the verify check are repeated. If a particular number of times of rewriting cannot achieve correct writing, a decision is made that the flash memory 1 is defective.
With such an arrangement, the conventional involatile memory has a problem in that the data write time is basically determined by the bus width of the data port 5, and hence it takes a long total time for a today's large capacity memory to achieve the data write. This is because when writing data from the tester 2 to the flash memory 1, or when carrying out the verify check of the data in the flash memory 1, the data must be divided into parts matching the width of the data port 5 to be transferred through it.